Research Notes

Stage 1 — Raw Materials: Quartz sand → ultra-pure polysilicon (11N purity) → single crystal silicon ingot (Czochralski process) → sliced 300mm wafers. Key suppliers: Wacker Chemie (Germany), Hemlock (US) for polysilicon; Shin-Etsu and SUMCO (Japan) dominate 300mm wafers. Stage 2 — Chip Design (EDA): Synopsys (SNPS) and Cadence (CDNS) are the two dominant EDA tool providers. Without EDA software, you cannot design any chip below 28nm. ARM Holdings provides CPU instruction set architecture; Nvidia designs its own GPU architecture (CUDA). Stage 3 — Photomasks: Circuit patterns etched onto glass stencils. Hoya and AGC (Japan) make EUV mask blanks. Carl Zeiss (Germany) makes EUV pellicles. KLA (KLAC) inspects masks. Stage 4 — Lithography (most critical): ASML (Netherlands) has monopoly on EUV (13.5nm wavelength, ~$380M/machine). EUV enables 7nm and below efficiently. DUV (193nm) from ASML/Nikon/Canon handles 28nm+, and 7nm with expensive multi-patterning. Stage 5 — Deposition + Etch (hundreds of steps): Applied Materials (AMAT) — CVD, ALD, PVD, CMP. Lam Research (LRCX) — plasma etch, ALD. Tokyo Electron (TEL) — etch, CVD, track. Stage 6 — Inspection at every critical step: KLA Corp (KLAC) — wafer defect inspection, overlay metrology, process control. Without KLA, yield collapses. Stage 7 — Specialty Materials: Photoresists (JSR, Shin-Etsu, TOK — all Japan). Specialty gases (Air Products, Linde, Air Liquide). CMP slurries (Entegris/ENTG, Fujimi). Stage 8 — Wafer Fab: TSMC 4N process for Nvidia GPU die. TSMC is sole provider of leading-edge logic for Nvidia, Apple, AMD, Qualcomm. Stage 9 — Advanced Packaging (CoWoS): TSMC packages the GPU die + HBM stacks on a silicon interposer using CoWoS (Chip on Wafer on Substrate). This is unique to TSMC. SK Hynix provides HBM3E memory stacks. Stage 10 — Test: Teradyne (TER) for logic test; Advantest (Japan) for memory/HBM test. For an Nvidia B200: Two GPU dies (TSMC 4NP) + HBM3E (SK Hynix) + CoWoS packaging (TSMC) + NVLink-C2C die-to-die interconnect.

China has leverage in raw materials, not in advanced manufacturing tools or design. GALLIUM (China ~80% of global supply): Used in GaN semiconductors, RF chips, LEDs, power devices. China imposed export controls August 2023. No major alternative supply exists short-term. Companies most exposed: RF chip makers, power device companies. GERMANIUM (China ~60%): Fiber optic cables, infrared optics, some semiconductor substrates. Export controls August 2023. TUNGSTEN (China ~80%): Sputtering targets used in physical vapor deposition (chip metallization). Latent leverage — not yet weaponized. ANTIMONY (China ~50%): Flame retardants, some compound semiconductors. Export controls August 2024. RARE EARTH ELEMENTS (China ~85% of processing): Magnets, phosphors, lasers. Critical for motors, speakers, EV batteries. China mines ~60% and processes ~85% globally. Less direct chip impact but critical for the broader electronics ecosystem. FLUORSPAR (China ~60%): Source material for hydrofluoric acid (HF) used extensively in chip etching. Less attention but real exposure. POLYSILICON (GCL Poly is world-largest): Primarily solar grade; electronics-grade still dominated by Wacker/Hemlock/Tokuyama. Less of a current leverage point. MATURE NODE CAPACITY: China is building enormous 28nm fabs (SMIC, Nexchip, Huali). By 2026-27 they will flood the market with cheap mature-node chips for automotive, IoT, industrial. This threatens Western foundries at mature nodes (GlobalFoundries, UMC) but not at advanced nodes. CONVENTIONAL PACKAGING: JCET and Tongfu are world-scale OSAT providers. China has real strength here for conventional (non-advanced) packaging. BOTTOM LINE: China's leverage is in the ground (minerals), not in the fab. Western strategy is to diversify materials sourcing (MP Materials, Energy Fuels) while maintaining tool + foundry dominance.

THE SUPREME CHOKEPOINTS (China completely blocked): 1. ASML (Netherlands, ASML) — EUV lithography. Only company on earth making EUV machines. China blocked since 2019. Advanced DUV (NXT:2000i+) also restricted since Jan 2024. Without EUV, China cannot efficiently make chips below 7nm. SMEE (China's domestic attempt) is at ~90nm; 28nm is a distant goal. 2. Synopsys (SNPS) + Cadence (CDNS) — EDA tools. Restricted from selling advanced EDA to Chinese chip designers. Without updated EDA, Chinese companies cannot design leading-edge chips. Their HiSilicon/Huawei designs are frozen on older tool versions. 3. TSMC (TSM) — advanced foundry. Stopped taking orders for advanced nodes from Chinese customers. SMIC cannot replace TSMC's sub-7nm capability. 4. SK Hynix / Micron (MU) — HBM memory. China has zero HBM capability (CXMT cannot make it). Huawei Ascend 910B uses LPDDR5 instead of HBM — severe bandwidth bottleneck for AI training. 5. Applied Materials (AMAT) + Lam Research (LRCX) + KLA (KLAC) — equipment. Restricted from selling advanced tools to China's cutting-edge fabs. Also restricted from SERVICING existing tools in China's advanced fabs — critical because these machines require constant calibration. 6. Japan aligned (Tokyo Electron TEL, JSR, Shin-Etsu, photoresist makers) — export controls on EUV photoresists, advanced equipment, specialty chemicals. HOW CHINA IS RESPONDING: - SMEE: Building domestic lithography (~90nm now, targeting 28nm). Faces fundamental physics + supply chain constraints on the laser source, optics (needs Zeiss-quality mirrors), and controls. - NAURA + AMEC: Domestic etch and CVD equipment. Genuine progress at mature nodes (28nm+). - SMIC 7nm via DUV multi-patterning: Achieved for Huawei Kirin 9000S (Mate 60 Pro, 2023). Technically impressive but low yield and expensive. Cannot scale below 5nm. - YMTC: NAND flash 232-layer. Actually competitive with Samsung/Micron at mature NAND. Not relevant for AI (which needs HBM, not NAND). - CXMT: DRAM at ~19nm vs Samsung/Hynix at 12nm. Significant gap. - Huawei Ascend 910B: Domestic AI chip, claims ~80% H100 training performance (disputed). Real weakness is no HBM — interconnect bandwidth is the wall. - RISC-V: Dozens of Chinese companies building RISC-V CPUs to escape ARM/x86 licensing. - Big Fund III (2024): ~$47B government investment fund for domestic semiconductor industry. - Hoarding: China stockpiled DUV tools, advanced memory, and Nvidia GPUs before each export control tightening. - Routing: Buying chips through Malaysia, Singapore, Middle East intermediaries (US cracking down on this). VERDICT: China is making real progress at 28nm+ mature nodes and in NAND flash. At advanced nodes (<7nm), HBM, and advanced packaging, the gap is widening not narrowing because the West keeps restricting more tools and China's domestic alternatives are 7-10 years behind.

HBM is the key memory technology that makes AI GPUs fast enough to be useful for training large models. WHY HBM EXISTS: A GPU's CUDA cores can process data faster than conventional DRAM (DDR5) can feed them. Standard DRAM is connected via a narrow bus. HBM solves this by stacking multiple DRAM dies vertically (using Through-Silicon Vias / TSVs) and placing them on the same silicon interposer as the GPU die via TSMC's CoWoS packaging. The "bus" becomes thousands of parallel connections just millimeters wide. SPECS COMPARISON: - DDR5: ~100 GB/s bandwidth - LPDDR5 (Huawei Ascend uses this): ~200 GB/s - HBM3E (H200): 5.4 TB/s — 27x more bandwidth than DDR5 For LLM training, the model weights must be constantly moved in and out of memory. Bandwidth = training speed. HBM is not optional for competitive AI training performance. SUPPLY CHAIN: SK Hynix (Korea) is the dominant HBM3E supplier and Nvidia's primary source. Samsung is qualifying HBM3E late. Micron (MU) is the US supplier — critical for national security diversification. TSMC does the CoWoS packaging that integrates HBM + GPU die. HBM4 (coming 2025-2026): SK Hynix and Samsung competing. Higher bandwidth, lower power. TSMC will do packaging. CHINA: CXMT (ChangXin Memory) makes DRAM at 19nm node. No TSV capability, no HBM. This is a complete wall for China's AI chip ambitions. Even if SMIC could make a competitive GPU die, there is no Chinese HBM to pair with it. The Ascend 910B's real-world AI training performance is severely limited by this.